Several practices, common in the prior art, tend to utilize resources in integrated circuits (ICs) in an inefficient manner. These are:
1. The use of metal level 2 for local interconnect. PA1 2. The use of metallization located above a row of transistors for interconnect for other transistors, rendering the row of transistors non-usable. PA1 3. The use of a cell spacing (or "row pitch") in a MACRO which is different from that of the rest of the array of standard cells into which the MACRO is embedded. PA1 1. The use of METAL 2 for local interconnect presents obstacles to the free routing of other interconnects over the cell, as illustrated in FIG. 3. PA1 2. In a standard cell array, the ROW PITCH is determined by the cell height and the number of lines of METAL 1 interconnect placed between the cell rows by the auto-router. PA1 3. The row pitch in a MACRO is generally different from that of a standard cell array into which the MACRO is embedded. This different row pitch disrupts the power bus system, requiring a ring of power busses to be formed around the MACRO. This approach wastes space within the IC.
These practices will be addressed individually.